In a simple binary counter, the CLK input of each flip-flop (except for the first one) is connected to the previous flip-flops _________?

In a simple binary counter, the CLK input of each flip-flop (except for the first one) is connected to the previous flip-flops _________?

• A. Q output
• B. Q' output
• C. Clock input
• D. Data input

Answer: (A)

In a simple asynchronous (ripple) binary counter, each flip-flop is a toggle cell. The least-significant bit is driven by the main clock, and the clock input of the next flip-flop is fed from the Q output of the previous stage. This setup makes the next stage toggle only when the previous stage changes state, so the higher bits flip at half the rate of the lower bits and in sequence to form a binary count. If you used the inverted output, the next stage would respond on the opposite edge, giving a different timing and wrong counting behavior. If you fed the next stage from the main clock, all stages would toggle together instead of in a staged ripple. The data input isn’t used for clocking in this configuration, so the Q output is the correct connection.

In a simple asynchronous (ripple) binary counter, each flip-flop is a toggle cell. The least-significant bit is driven by the main clock, and the clock input of the next flip-flop is fed from the Q output of the previous stage. This setup makes the next stage toggle only when the previous stage changes state, so the higher bits flip at half the rate of the lower bits and in sequence to form a binary count. If you used the inverted output, the next stage would respond on the opposite edge, giving a different timing and wrong counting behavior. If you fed the next stage from the main clock, all stages would toggle together instead of in a staged ripple. The data input isn’t used for clocking in this configuration, so the Q output is the correct connection.